In the field of telecommunications, Phase Locked Loops (PLLs) are used to generate clock signals based on filtered incoming reference clock signals. When the PLL output is following the reference input, this is referred to as the normal Locking mode. When a disturbance causes the incoming reference signal to be disqualified, the PLL goes into holdover mode based on a memorized frequency. This memorized frequency is of a certain age such that under normal circumstances it was stored before the disturbance on the reference clock occurred.
When the PLL is in holdover mode and the reference is again qualified, the PLL may switch back to the normal locking mode. When this happens, the output frequency is again taken from the PLL filter. The frequency stored in the PLL filter however will be not identical to the holdover frequency and this will cause a frequency step on the output. In most cases this step will be very small and within acceptable limits, but under certain conditions (e.g. in the presence of frequency slope limiters in the filter) it can get larger.